1. Field of the Invention
The present disclosure generally relates to the manufacture of integrated circuits, and, more particularly, to methods of forming a semiconductor structure wherein ion implantation processes are performed to form dopant profiles adjacent features formed on a semiconductor substrate.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements such as, e.g., transistors, capacitors and resistors. These elements are connected internally to form complex circuits such as memory devices, logic devices and microprocessors. The performance of integrated circuits may be improved by increasing the number of functional elements per circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Field effect transistors are used as switching elements in integrated circuits. They provide a means to control a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
A method of forming a semiconductor structure comprising field effect transistors according to the state of the art will be described in the following with reference to FIGS. 1a-1c. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of the method according to the state of the art.
The semiconductor structure 100 comprises a substrate 101. A first transistor element 102, comprising an active region 104, a gate electrode 106 and a gate insulation layer 105, providing electrical insulation between the gate electrode 106 and the active region 104, is formed in the substrate 101. The gate electrode 106 may have a top surface 117 and a side surface 118. An extended source region 107 and an extended drain region 108 are formed adjacent the gate electrode 106. The substrate 101 further comprises a second transistor element 202. Similar to the first transistor element 102, the second transistor element 202 comprises an active region 204, a gate electrode 206, having a top surface 217 and a side surface 218, a gate insulation layer 205, an extended source region 207 and an extended drain region 208. A trench isolation structure 103 provides electrical insulation between the first transistor element 102 and the second transistor element 202.
The above-described features may be formed by means of methods of photolithography, etching, deposition, oxidation and ion implantation, well known to persons skilled in the art. In particular, the active regions 104, 204, the extended source regions 107, 207 and the extended drain regions 108, 208 may be formed by means of known ion implantation processes wherein the semiconductor structure 100 is irradiated with ions of a dopant material. In some examples of methods of forming a semiconductor structure according to the state of the art, the first transistor element 102 may be a P-type transistor and the second transistor element 202 may be an N-type transistor. In such embodiments, ions of a P-type dopant may be implanted into the extended source region 107 and the extended drain region 108 of the first transistor element 102, and ions of an N-type dopant may be implanted into the extended source region 207 and the extended drain region 208 of the second transistor element 202. In each of these implantation processes, one of the transistor elements 102, 202 may be covered with a mask comprising, for example, a photoresist, while ions are implanted into the other of the transistor elements 102, 202. The masks may be formed by means of techniques of photolithography well known to persons skilled in the art.
A layer 109 comprising a first material and a layer 110 comprising a second material may then be formed over the semiconductor structure 100. In some examples of methods according to the state of the art, the layer 109 may comprise silicon nitride and the layer 110 may comprise silicon dioxide. The layers 109, 110 may be formed by means of well-known deposition processes such as chemical vapor deposition (CVD) and/or plasma enhanced chemical vapor deposition (PECVD).
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process according to the state of the art. After the formation of the layers 109, 110, an anisotropic etch process may be performed wherein the semiconductor structure 100 is exposed to an etchant adapted to selectively remove the material of the layer 110, leaving the material of the layer 109 substantially intact. In some examples of prior art manufacturing processes, the anisotropic etch process may comprise a known dry etch process.
As persons skilled in the art know, in anisotropic etching, substantially horizontal portions of the layer 110 of second material, such as, for example, portions over the extended source regions 107, 207, the extended drain regions 108, 208 and the top surfaces 117, 217 of the gate electrodes 106, 206, are etched at a greater etch rate than portions of the layer 110 being inclined or substantially vertical, such as portions over the side surfaces 118, 218 of the gate electrodes 106, 206.
The anisotropic etch process may be stopped upon a substantial removal of the portions of the layer 110 of the second material over the horizontal portions of the semiconductor structure 100. Thus, portions of the layer 110 may remain on the semiconductor structure 100 to form sidewall spacer structures 111, 211 adjacent the gate electrode 106 of the first transistor element 102 and the gate electrode 206 of the second transistor element 202.
Thereafter, the first transistor element 102 may be covered with a mask 112. The mask 112 may comprise a photoresist, and may be formed by means of techniques of photolithography well known to persons skilled in the art.
FIG. 1c shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process according to the state of the art. After the formation of the mask 112, an etch process, wherein the semiconductor structure 100 is exposed to an etchant adapted to selectively remove the second material in the sidewall spacer structures 111, 112, may be performed. In examples of methods of forming a semiconductor structure wherein the second material comprises silicon dioxide, the etch process may be a wet etch process wherein the semiconductor structure 100 is exposed to diluted hydrofluoric acid.
The etch process may remove the sidewall spacer structure 211 adjacent the gate electrode 206 of the second transistor element 202. The first transistor element 102, however, may be protected from being affected by the etchant by the mask 112. Therefore, the sidewall spacer structure 111 adjacent the gate electrode 106 of the first transistor element 102 remains on the semiconductor structure 100. After the etch process, the mask 112 may be removed by means of a known resist strip process.
Subsequently, a further anisotropic etch process, which may, in some examples of methods of forming a semiconductor structure according to the state of the art, comprise a dry etch process, may be performed. An etchant used in the anisotropic etch process may be adapted to selectively remove the first material in the layer 109, leaving the second material in the sidewall spacer structure 111 adjacent the gate electrode 106 of the first transistor element 102 substantially intact.
The anisotropic etch process may be stopped upon a substantial removal of portions of the layer 109 of the first material over horizontal portions of the semiconductor structure 100. In particular, portions of the layer 109 over the extended source regions 107, 207, the extended drain regions 108, 208 and the top surfaces 117, 217 of the gate electrodes 106, 206 may be substantially removed. Portions of the layer 109 over the sidewalls 118, 218 of the gate electrodes 106, 206, however, may remain on the semiconductor structure 100 to form a sidewall spacer structure 113 adjacent the gate electrode 106 and a sidewall spacer structure 213 adjacent the gate electrode 206.
Thus, in the method of forming a semiconductor structure according to the state of the art, two sidewall spacer structures 113, 111 are formed adjacent the gate electrode 106 of the first transistor element 102, and a single sidewall spacer structure 213 is formed adjacent the gate electrode 206 of the second transistor element 202.
After the formation of the sidewall spacer structures 111, 113, 213, an ion implantation process may be performed to form a source region 114 and a drain region 115 adjacent the gate electrode 106. In the ion implantation process, the semiconductor structure 100 may be irradiated with ions of a dopant material. The second transistor element 202 may be covered by a mask (not shown) during the ion implantation process. The sidewall spacer structures 113, 111 may absorb ions impinging on the sidewall spacer structures 113, 111 such that the source region 114 and the drain region 115 are spaced apart from the gate electrode 106 by a distance 116 corresponding to the combined thickness of the sidewall spacer structures 113, 111.
A further ion implantation process may be performed to form a source region 214 and a drain region 215 adjacent the gate electrode 206 of the second transistor element 202. A mask (not shown) may be formed over the first transistor element 102 to protect the first transistor element 102 from being irradiated with ions. The sidewall spacer structure 213 may absorb ions impinging on the sidewall spacer structure 213 such that the source region 214 and the drain region 215 are spaced apart from the gate electrode 206 by a distance 216 corresponding to the thickness of the sidewall spacer structure 213.
The distance 216 may be smaller than the distance 116. Therefore, compared to the source and drain regions 214, 215 of the second transistor element 202, the source and drain regions 114, 115 of the first transistor element 102 may be provided at a greater distance to the gate electrode of the respective transistor element. In examples of manufacturing processes according to the state of the art wherein the first transistor element 102 is a P-type transistor and the second transistor element 202 is an N-type transistor, this may allow an adaptation of the dopant profiles in the transistor elements 102, 202 to the specific properties of P-type and N-type dopants, respectively.
A problem of the above-described method of forming a semiconductor structure according to the state of the art is that a photolithography process is required to form the mask 112 such as to obtain a different spacing between the source and drain regions, respectively, and the gate electrode in the first and the second transistor element. In addition to the photolithographic process performed in the formation of the mask 112, two further photolithographic processes may be required to form masks covering the transistor elements 102, 202 during the ion implantation processes performed to create the source regions 114, 214 and the drain regions 115, 215. Hence, in summary, the formation of the source regions 114, 214 and the drain regions 115, 215 may comprise three photolithographic processes. As persons skilled in the art know, photolithographic processes may contribute significantly to the cost and complexity of the manufacturing process, since photolithography may require costly and complex tools providing the high degree of precision and working accuracy required in advanced semiconductor manufacturing technology. Hence, the above-described method of forming a semiconductor structure may be relatively expensive and time-consuming.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.